1.Technical Field
This description generally relates to the field of integrated circuits, and more particularly to chip packaging for integrated circuits.
2.Description of the Related Art
In many compact electronic devices, there is less and less room to accommodate bulky chip packages. As a result, a number of manufacturers have begun stacking chip packages on top of one another to form “package-on-package” solutions. Such chip packages may comprise, for example, a top chip package holding a memory subsystem stacked on top of a bottom chip package carrying logic circuitry. The memory and logic package-on-package may take up little more room than the logic chip package alone.
In FIG. 1, a schematic view of one exemplary bottom chip package 1 that might be incorporated into a package-on-package is illustrated. FIG. 2 illustrates a schematic, cross-sectional view of the bottom chip package 1 alone, and FIG. 3 illustrates a cross-sectional view of the bottom chip package 1 coupled to a top chip package 2 in a package-on-package 3. As illustrated in FIGS. 1 and 2, a conventional bottom chip package 1 may include a substrate 10 on which an integrated circuit 12 is mounted. The integrated circuit 12 may then be encapsulated by an encapsulant to form a cap 14, leaving bond pads 16 exposed around the perimeter of the bottom chip package 1 to form electrical connections with the top chip package 2.
Unfortunately, in many package-on-package products, the bottom chip package may suffer from poor coplanarity. That is, with reference to FIG. 2, the left and right edges of the substrate 10 may curve up or down in what is known as smiling or crying warpage, respectively. Such coplanarity may worsen as the bottom chip package 1 undergoes thermal processing during manufacture of the package-on-package 3. This poor coplanarity of the bottom chip package 1 may result in high yield loss and bad solder joint quality and reliability between the bottom chip package 1 and the top chip package 2. There is therefore a need in the art for a chip package with improved coplanarity.